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│ ◈ ENGINEER Harsh Saini │
│ ◈ DISCIPLINE Hardware Design · Power Electronics · PCB Engineering │
│ ◈ CURRENT ROLE Hardware Design Engineer — Winet Infratel (R&D) │
│ ◈ ACADEMIC B.Tech — Electronics & Communication Engineering │
│ │
│ ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━ │
│ │
│ PRESENT ▸ EVSE Systems · SMPS · Multi-layer PCB · Embedded Control │
│ VECTOR ▸ Signal Integrity · Power Integrity · High-Speed Digital │
│ FRONTIER ▸ DDR · PCIe · Ethernet · PDN · Controlled Impedance │
│ │
└─────────────────────────────────────────────────────────────────────────────────┘
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Topologies:
- Synchronous Buck
- Flyback (Isolated)
- SMPS Architecture
EVSE Systems:
- IEC 61851 / 62196
- Control Pilot
- SAE J1772
Protection:
- OVP / UVP / OCP
- Gate Drive Design
- Thermal Analysis |
Layout:
- 1L to 6L Boards
- Stackup Planning
- Impedance Control
- Differential Pairs
Manufacturing:
- Gerber / NC Drill
- BOM / CPL
- DFM / DFT
- Assembly Support
Practice:
- EMI-Aware Layout
- Via Stitching
- Thermal Reliefs |
Controllers:
- ESP32 (Wi-Fi/BT)
- ARM Cortex (basic)
Interfaces:
- UART / SPI / I2C
- CAN Bus
- USB Full-Speed
Firmware:
- Embedded C
- Peripheral Drivers
- State Machines
- Interrupt Logic |
Signal Integrity:
- Transmission Lines
- Return Path Design
- Crosstalk Control
- Diff Pair Routing
- Length Matching
- Termination
Power Integrity:
- PDN Architecture
- Target Impedance
- Decoupling Hierarchy
- SSN Mitigation
High-Speed:
- DDR Interfaces
- PCIe Fundamentals
- Ethernet Layout |
─── PCB Design Platforms ───
─── Simulation & Analysis ───
─── Embedded & Programming ───
─── Interfaces & Protocols ───
─── High-Speed Systems — Active Study ───
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Power Electronics
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PCB Engineering
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High-Speed — Study Frontier
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01 · 7.4 kW EVSE Charger System — Winet Infratel R&D · IEC 61851 / IEC 62196
┌─ SYSTEM SPECIFICATION ──────────────────────────────────────────────────────┐
│ Output Power : 7.4 kW — Single-phase AC │
│ Standard : IEC 61851-1 / IEC 62196 / SAE J1772 │
│ Connector : Type-2 Mennekes │
│ Controller : ESP32 custom control PCB │
│ Protection : GFCI · OVP · OCP · Relay state feedback │
│ Interface : Control Pilot — PWM duty-cycle modulation │
└─────────────────────────────────────────────────────────────────────────────┘
Challenge: Implementing a hardware-validated, standards-compliant EVSE state machine with precision control pilot waveform generation and fail-safe relay sequencing.
Engineering Constraints: Clearance/creepage isolation requirements. High-voltage domain separation. EMC compliance for AC-connected equipment.
Design Decisions: Isolated control pilot generation using optocoupler and precision timer. MOSFET + relay combination for contact protection. Bidirectional relay feedback for state verification before current enable.
PCB Considerations: Primary/secondary domain split with optical isolation boundary. Creepage distances maintained per IEC 60950. Thermal dissipation calculated for 7.4 kW continuous. EMI input filtering on AC stage.
Validation: Oscilloscope-verified pilot waveforms across all EV states (A/B/C/D). Timing validated per IEC 61851 state transition requirements. Load testing under rated condition.
Lessons Learned: Control pilot impedance matching critical for accurate state detection. Relay bounce suppression firmware essential for reliable sequencing. PCB ground planes must not split across control pilot return path.
02 · 120W Synchronous Buck Converter — TI LM5116 · High-Efficiency DC-DC
┌─ SYSTEM SPECIFICATION ──────────────────────────────────────────────────────┐
│ Controller IC : Texas Instruments LM5116 │
│ Topology : Synchronous Buck │
│ Output Power : 120W │
│ Key Focus : Loop compensation · PCB switching noise minimization │
└─────────────────────────────────────────────────────────────────────────────┘
Challenge: Achieving stable regulation across full load range while minimizing switching noise coupling into the sensitive feedback network.
Engineering Constraints: High dv/dt switching node requiring contained loop area. Type-III compensation network design for adequate phase margin.
Design Decisions: Kelvin sensing at output capacitor terminals for regulation precision. Bootstrap and gate drive loops minimized. Top and bottom FET placed symmetrically around the switching node.
PCB Considerations: High-frequency current loop (input cap → top FET → inductor → output cap) area minimized to sub-cm² routing. Feedback network placed in quiet ground zone, away from switching node. Analog ground island under error amplifier.
Validation: Efficiency curve measured across 10%–100% load. Load transient step captured at ±50% load change. Phase and gain margin verified under operating temperature range.
Lessons Learned: Kelvin sense routing critically affects regulation accuracy under load. Ground plane integrity under the gate driver is essential for clean switching transitions.
03 · 60W Isolated Flyback SMPS
┌─ SYSTEM SPECIFICATION ──────────────────────────────────────────────────────┐
│ Topology : Flyback — transformer-isolated │
│ Output Power : 60W │
│ Feedback : Optocoupler + TL431 error amplifier │
│ Isolation : Primary / secondary galvanic separation │
└─────────────────────────────────────────────────────────────────────────────┘
Challenge: Achieving tight output regulation across full line and load variation while suppressing transformer leakage spike energy.
Engineering Constraints: Galvanic isolation requirement. Leakage inductance spike clamping. Feedback loop stability across optocoupler CTR variation.
Design Decisions: RC-D snubber network dimensioned to clamp leakage spike within MOSFET VDS rating with margin. Optocoupler feedback compensation designed for stable crossover frequency with adequate phase margin.
PCB Considerations: Primary/secondary grounds separated — single-point connection at input filter. Creepage distances maintained per IEC 60950. Snubber placed immediately adjacent to transformer primary terminal. No signal traces cross isolation boundary without optical or capacitive coupling.
Validation: Regulation accuracy tested across 90–265V AC input and 10%–100% load. Switching node captured to confirm snubber effectiveness. No oscillation under line and load step events.
Lessons Learned: Physical snubber placement proximity to transformer directly impacts leakage spike amplitude. Optocoupler pole must be included in compensation model.
04 · 2S Lithium Battery Management System
┌─ SYSTEM SPECIFICATION ──────────────────────────────────────────────────────┐
│ Configuration : 2S Lithium cell pack │
│ Protections : OVP · UVP · OCP — per cell and pack │
│ Switching : Back-to-back N-MOSFET (bidirectional) │
│ Sensing : Dedicated shunt resistor + fast comparator │
└─────────────────────────────────────────────────────────────────────────────┘
Challenge: Implementing reliable bidirectional protection with independent charge/discharge FET control and sub-millisecond OCP response.
Engineering Constraints: Back-to-back MOSFET body diode management. Shunt resistor measurement accuracy under high current. Cell voltage sensing accuracy without common-mode error.
Design Decisions: Back-to-back N-MOSFET for bidirectional path control. Dedicated sensing resistor with Kelvin connection to minimize resistance error. Hysteresis added to voltage threshold comparators for clean switching without chatter.
PCB Considerations: Current path traces sized for peak discharge with derating. Shunt resistor Kelvin connections routed independently of current-carrying traces. MOSFET thermal pad attached to copper pour with thermal vias.
Validation: OVP and UVP trigger thresholds verified with precision bench supply. OCP cutoff timing validated with electronic load current step. Re-enable behavior confirmed across multiple charge-discharge cycles.
Lessons Learned: Shunt Kelvin routing is critical — any shared impedance with the current path introduces offset error. Body diode reverse recovery in back-to-back configuration must be evaluated under transient conditions.
05 · ESP32 HRV Monitoring System — Biometric Embedded Hardware
┌─ SYSTEM SPECIFICATION ──────────────────────────────────────────────────────┐
│ MCU : ESP32 — Xtensa dual-core 240 MHz │
│ Sensor : MAX30102 — PPG / SpO2 / HRV │
│ Interface : I2C 400 kHz Fast Mode │
│ Output : Real-time biometric acquisition over Wi-Fi │
└─────────────────────────────────────────────────────────────────────────────┘
Challenge: Placing a noise-sensitive analog PPG sensor on the same board as a high-frequency Wi-Fi/BT radio (ESP32) without degrading signal quality.
Engineering Constraints: MAX30102 sensitive to supply noise and ground bounce. ESP32 RF switching generates broadband interference. I2C signal integrity at 400 kHz requires controlled rise/fall times.
Design Decisions: Analog and digital ground domains separated with single star-point connection. Individual decoupling at MAX30102 VCC and LED drive pins. I2C pull-up values optimized for 400 kHz rise time per NXP I2C specification. Interrupt-driven acquisition for precise timing.
PCB Considerations: MAX30102 placed maximally distant from ESP32 RF domain and antenna keep-out zone. AGND copper pour under sensor isolated from DGND by moat. SDA/SCL traces kept under 30mm and away from RF area.
Validation: I2C waveform captured — rise and fall times confirmed within spec at 400 kHz. HRV data cross-validated against clinical reference device. Power consumption profiled in deep sleep, acquisition, and transmission modes.
Lessons Learned: AGND/DGND separation is non-negotiable on mixed-signal boards with integrated RF. Antenna keep-out enforcement prevents I2C clock corruption during Wi-Fi transmit bursts.
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║ SIGNAL INTEGRITY FRAMEWORK ║
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║ FOUNDATIONS ROUTING TECHNIQUES SYSTEM INTERFACES ║
║ ────────────── ──────────────────── ───────────────── ║
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║ Transmission Lines Differential Pairs DDR Memory ║
║ ├─ Z0 definition ├─ Edge coupled ├─ Fly-by topology ║
║ ├─ Propagation delay ├─ Length matching ├─ Write leveling ║
║ ├─ Reflection coefficient ├─ Common-mode rejection ├─ DQ/DQS groups ║
║ └─ Termination strategies └─ Skew control └─ Eye margin ║
║ ║
║ Return Path Analysis Crosstalk Control PCIe / Ethernet ║
║ ├─ Ground plane continuity ├─ 3W rule enforcement ├─ SERDES budget ║
║ ├─ Split plane effects ├─ Guard trace usage ├─ Pre-emphasis ║
║ ├─ Via return paths ├─ Layer assignment ├─ Lane equalization ║
║ └─ Stitching capacitors └─ Aggressor analysis └─ Ref plane rules ║
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╠═══════════════════════════════════════════════════════════════════════════════╣
║ POWER INTEGRITY FRAMEWORK ║
╠═══════════════════════════════════════════════════════════════════════════════╣
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║ PDN Architecture Decoupling Hierarchy Simulation Chain ║
║ ├─ Target impedance Zt ├─ Bulk electrolytic ├─ LTspice PDN ║
║ ├─ VRM placement/BW ├─ Mid-frequency ceramic ├─ Z vs frequency ║
║ ├─ Plane capacitance ├─ High-freq 0402/0201 ├─ MATLAB Bode ║
║ └─ SSN / delta-I noise └─ Placement proximity └─ HyperLynx (next) ║
║ ║
╚═══════════════════════════════════════════════════════════════════════════════╝
B.Tech — Electronics PCB Design Power Electronics
& Communication Engg Multi-layer Layout SMPS / Buck / Flyback
────────────── ───────────── ─────────────────────
│ │ │
▼ ▼ ▼
──────●────────────────────────────●──────────────────────────●────────────▶
│ │ │
│ Embedded │ EVSE Systems │ SI / PI
│ Systems │ IEC 61851 │ High-Speed
│ ESP32 / CAN │ 7.4 kW │ DDR · PCIe
│ ─────────── │ ──────────── │ ──────────
▼ ▼ ▼
Foundation Production Frontier ──────▶
╔═══════════════════════════════════════════════════════════════════════════════╗
║ ║
║ "Physics never negotiates. ║
║ Reliable hardware emerges from disciplined engineering." ║
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║ ───────────────────────────────────────────────────────────────────────── ║
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║ Every uncontrolled impedance discontinuity is a reflection event. ║
║ Every interrupted return path is noise already inside the system. ║
║ Every underdamped PDN is a timing failure waiting for the right load. ║
║ Every thermal assumption not validated is a field return. ║
║ ║
║ Hardware does not fail randomly. It fails predictably. ║
║ Know the physics. Control the failure modes. ║
║ ║
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Open to opportunities in:
Hardware Design · Signal Integrity · Power Integrity
PCB Engineering · EMI / EMC · High-Speed Digital Systems
Semiconductor Hardware · Platform Engineering